1. Field of the Disclosure
The present disclosure is generally directed to a processor system and, more particularly, to techniques for accessing a resource in a processor system.
2. Description of the Related Art
In a typical computer system, memory controllers are implemented within a Northbridge chip (integrated circuit (IC)) or within a central processing unit (CPU) chip (in order to reduce memory latency). In general, memory controllers manage the flow of data to/from a memory. Dynamic random access memory (DRAM) controllers contain logic necessary to read data from and write data to DRAM modules and to refresh the DRAM modules. As is well known, without periodic refreshes, DRAM modules lose written data, as capacitors internal to the DRAM modules leak current. Memory controller bus widths have ranged from 8-bits (in relatively simple memory subsystems) to 256-bits (in more complicated memory subsystems and video cards). In a typical computer system, DRAMs are organized in channels of dual in-line memory modules (DIMMs), with each DIMM supporting some number of ranks (or chip selects) and each chip select some number of banks. In general, such an organization increases the command and data bandwidth of a memory subsystem by supporting multiple parallel transactions to different DRAM banks.
Typically, computer systems that have employed conventional memory controllers have implemented relatively complex logic to control access (i.e., schedule commands on a DRAM bus) to all DRAM modules that may be present in a computer system, even when one or more DRAM module slots are not populated in the computer system. In a typical application, a memory controller has attempted to schedule commands on the DRAM bus to maximize data bandwidth, reduce bus turn-around time, and minimize latency associated with reads/writes from/to memory. To efficiently access DRAM, memory controllers have usually performed out-of-order scheduling of requests (e.g., reads/writes). In general, conventional DRAM scheduling algorithms have attempted to choose a best possible DRAM command stream by tracking a state that corresponds to a maximum channel configuration (i.e., conventional DRAM controllers have employed a flat structure). Using this approach has required relatively complex scheduling logic that has generally consumed a relatively large die area (and correspondingly has increased power requirements). Typically, reads/writes to an active (open) page or row of a memory bank (i.e., page hits) have been given priority over reads/writes to an inactive (closed) page or row of a memory bank (i.e., page misses), which have been given priority over reads/writes to a page or row of a memory bank that is different from a currently active (open) page or row (i.e., page conflicts) of the memory bank.
What is needed is a scalable dynamic random access memory (DRAM) scheduling technique (for accessing DRAM present in a processor system) that readily facilitates tracking less than a maximum channel configuration when desired.
The use of the same reference symbols in different drawings indicates similar or identical items.